Journal Papers
74. You-Rong Chen, Chien-Chia Ho, Wei-Ting Chen, and Pei-Yin Chen, “A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm”, IEEE Transactions on Circuits and Systems I: Regular Papers vol. 71, no.2, pp. 717-730, Feb. 2024 (SCI).
73. Shih-Hsiang Lin, Jun-Yi Lee, Chia-Chou Chuang, Narn-Yih Lee, Pei-Yin Chen*, Wen-Long Chin, “Hardware Implementation of High-Throughput S-Box in AES for Information Security”, IEEE Access vol. 11, pp. 59049-59058, June. 2023 (SCI).
72. Chi-Ting Ni, Ying-Chia Huang, and Pei-Yin Chen, “A Hardware-Friendly and High-Efficiency H.265/HEVC Encoder for Visual Sensor Networks”, Sensors vol. 23, no. 5, Mar. 2023 (SCI).
71. Kuan-Yu Huang, Suraj Pramanik and Pei-Yin Chen, “A Cost-Effective Interpolation for Multi-Magnification Super-Resolution”, IEEE Access vol. 10, pp. 102076-102086, Oct. 2022 (SCI).
70. Chi-Ting Ni, Shih Hsiang Lin, Pei-Yin Chen and Yu-Ting Chu, “High Efficiency Intra CU Partition and Mode Decision Method for VVC”, IEEE Access vol. 10, pp.77759-77771, Aug. 2022 (SCI).
69. You-Rong Chen*, Wei-Ting Chen, Shao-Chieh Liao, Pei-Yin Chen, Hong-Yu Fang and Tzu-You Tai, “A High-Speed Low-Cost Hardware Implementation for Depth Estimation Using Disparity Fusion Method”, IEEE Access vol. 10, pp.72850-72865, Aug. 2022 (SCI).
68. You-Tun Teng, Wen-Long Chin, Deng-Kai Chang, Pei-Yin Chen and Pin-Wei Chen, “VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic”, IEEE Access vol. 10, pp. 2721-2728, Jan. 2022 (SCI).
67. Y.-H. Shiau, K.-Y. Huang, P.-Y. Chen and C.-Y. Kuo, “A Low-cost Hardware Design of Learning-based One-dimensional Interpolation for Real-time Video Applications at the Edge,”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems vol. 11, no. 4, pp. 677-689, Dec. 2021 (SCIE).
66. Shao-Chieh Liao, Pei-Yin Chen, Jiun-Hung Lin, Julie Chi Chow, Willy Chou, and Yan-Jhen Huang, “Infants’ crying sounds at pain stimuli from injections: analysis of time-frequency domain and correlation with temperament”, Biomedical Engineering-Applications Basis Communications vol. 33, no. 3, Jun 2021.
65. Wei-Ting Chen, Ren-Der Chen, Pei-Yin Chen, and Yu-Che Hsiao, “A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm”, IEEE Transactions on Circuits and Systems I: Regular Papers vol. 68, no. 4, pp.1493-1506, Apr 2021.
64. Ing-Chao Lin, Wei-Ting Chen, Yu-Cheng Chou and Pei-Yin Chen, “A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network”, IEEE Transactions on Circuits and Systems II: Express Briefs vol. 68, no. 4, pp.1413-1417, Apr 2021.
63. Ing-Chao Lin, Chi-Huan Tang, Chi-Ting Ni, Xing Hu, Yu-Tong Shen, Pei-Yin Chen, and Yuan Xie, “A Novel Comparison-Free 1D Median Filter”, IEEE Transactions on Circuits and Systems II: Express Briefs vol.67, no.7, pp.1329-1333, July 2020.
62. Shao Chieh Liao, Willy Chou, Jiun Hung Lin, Pei Yin Chen and Julie Chi Chow, “Investigation of the early prediction of infants’ temperament based on infant cries evoked by external pain stimuli”, Early Child Development and Care vol.190, no.8, pp.1286-1298, Jun 2020.
61. Da-Huei Lee, Pei-Yin Chen, Fu-Jhong Yang and Wan-Ting Weng, “High-Efficient Low-Cost VLSI Implementation for Canny Edge Detection”, Journal of Information Science and Engineering vol.36, no.3, pp.535-546, May 2020.
60. Yao-Tsung Kuo, Pei-Yin Chen and Hong-Cheng Lin, ”A Spatiotemporal Content-Based CU Size Decision Algorithm for HEVC”, IEEE Transaction on Broadcasting vol. 66, no. 1, pp.100-112, Mar 2020.
61. Chih-Yuan Lien, Chi-Huan Tang, Pei-Yin Chen, Yao-Tsung Kuo, and Yue-Ling Deng, “A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising”, IEEE Access vol.8, pp.64278-64283, Mar 2020.
58. Yeu-Horng Shiau, Yao-Tsung Kuo, Pei-Yin Chen, and Feng-Yuan Hsu, “VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications,”, IEEE Trans. on Circuits and Systems for Video Technology vol. 29, no. 1, pp. 238-251, Jan. 2019 (SCI, impact factor:3.558).
57. Shih-Hsiang Lin, Pei-Yin Chen, and Chang-Hsing Lin, “Hardware Design of an Energy-Efficient High-Throughput Median Filter,”, IEEE Transactions on Circuits and Systems II: Express Briefs vol. 65, no. 11, pp. 1728-1732, Nov. 2018 (SCI, impact factor:2.450).
56. Min-Chun Hu, Kiat Siong Ng, and Pei-Yin Chen, , “Local Binary Pattern Circuit Generator With Adjustable Parameters for Feature Extraction,” , IEEE Trans. on Intelligent Transportation Systems, vol. 19, no. 8, pp. 2582-2591, Aug. 2018 (SCI, impact factor:4.051).
55. Chih-Yuan Lien, Fu-Jhong Yang, and Pei-Yin Chen, “Efficient VLSI Architecture for Edge-Oriented Demosaicking”, IEEE Trans. on Circuits and Systems for Video Technology vol. 28, no. 8, pp. 2038-2047, Aug. 2018 (SCI, impact factor:3.558).
54. Ying-Hao Yu, Tsu-Tian Lee, and Pei-Yin Chen, “On-chip real-time feature extraction using semantic annotations for object recognition,” , Journal of Real-Time Image Processing,vol. 15, no. 2, pp. 249-264, Aug. 2018 (SCI, impact factor:1.574).
53. Shih-Hsiang Lin, Pei-Yin Chen,and Chih-Kun Hsu,“Modular Design of High-Efficiency Hardware Median Filter Architecture”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS vol. 65, no. 6, pp. 1929-1940, Jun. 2018.
52. Pei-Yin Chen, Shih-Hsiang Lin, and Po-Chun Chen, “Hardware Implementation of an Image Interpolation Method with Controllable Sharpness”, JOURNAL OF INFORMATION SCIENCE AND ENGINEERING vol. 34, no. 1, pp. 51-64, Jan. 2018.
51. Chih-Yuan Lien, Fu-Jhong Yang, and Pei-Yin Chen, “An Efficient Edge-Based Technique for Colour Filter Array Demosaicking”, IEEE Sensors Journal, vol. 17, no. 13, pp. 4067-4074, Jul. 2017.
50. Shih-Hsiang Lin, Pei-Yin Chen, and Yu-Ning Lin, “Hardware Design of Low-Power High-Throughput Sorting Unit”, IEEE Transactions on Computers, vol. 66, no. 8, pp. 1383-1395, Aug. 1 2017.
49. Pei-Yin Chen, Yen-Chen Lai, and Ping-Hsuan Lai, “Hardware Implementation of Local Mean Decomposition”, Journal of Information Science and Engineering, vol. 33, no. 1, pp. 51-62, Jan. 2016.
48. Pei-Yin Chen, Yen-Chen Lai, and Ju-Yang Zheng, “Hardware Design and Implementation for Empirical Mode Decomposition”, IEEE Transactions on Industrial Electronics, vol. 63, no. 6, pp. 3686-3694., Jun. 2016.
47. Chun-Hsien Yeh, Pei-Yin Chen, Chia-Hao Li, Hao-Ting Lin, Yen-Chen Lai, and Pei-Hua Chang, “Real-Time Digital Hardware Simulation of the Rodless Pneumatic System”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 9, pp. 853-857, Sep. 2016.
46. Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, and Shang-Yuan Li, “A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications”, IEEE Transactions on Intelligent Transportation System, vol. 16, no. 2, pp. 934-946, Apr. 2015.
45. Ren-Der Chen, Pei-Yin Chen, and Chun-Hsien Yeh, “A Low-Power Architecture for the Design of a One-Dimensional Median Filter,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 3, pp. 266-270, Mar. 2015.
44. Wei-Hsun Lee, Yen-Chen Lai, and Pei-Yin Chen, “A Study on Energy Saving and CO2 Emissions Reduction on SignalCountdown Extension by Vehicular Ad-Hoc Network,” IEEE Transactions on Vehicular Technology, vol. 64, no. 3, pp. 890-900, Mar. 2015.
43. Pei-Yin Chen, Chien-Chuan Huang, Chih-Yuan Lien,and Yu-Hsien Tsai, “An Efficient Hardware Implementation of HOG Feature Extraction for Human Detection,” IEEE Transactions on Intelligent Transportation System, Vol. 15, Issue. 2, pp. 656-662, Apr. 2014.
42. Y.-H.Shiau, P.-Y.Chen, H.-Y.Yang, C.-H.Chen, and S.-S.Wang, “Weighted haze removal method with halo prevention,” Journal of Visual Communication and Image Representation, Vol. 25, Issue. 2, pp. 445-453, Feb. 2014.
41. Ren-Der Chen, Pei-Yin Chen and Chun-Hsien Yeh, “Design of an Area-Efficient One-Dimensional Median Filter,” IEEE Trans. on Circuits Syst—II: Express Briefs, Vol. 60, No. 10, OCT 2013.
40. Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen,and Ya-Zhu Chuang, “Hardware Implementation of a Fast and Efficient Haze Removal Method,” IEEE Trans. on Circuits Syst. Video Technol, vol.23, no.8, pp. 1369-1374, Aug 2013.
39. Chih-Yuan Lien, Chien-Chuan Huang, Pei-Yin Chen, and Yi-Fan Lin, “An Efficient Denoising Architecture for Removal of Impulse Noise in Images,” IEEE Trans. on Computer, vol. 62, no. 04, pp. 631-643, April. 2013.
38. Chien-Chuan Huang, Pei-Yin Chen, and Ching-Hsuan Ma, “A Novel Interpolation Chip for Real-Time Multimedia Applications,” IEEE Trans. on Circuits Syst. Video Technol, vol. 22, no. 10, pp. 1512-1525, Oct. 2012.
37. Yeu-HorngShiau, Hung-Yu Yang, Pei-Yin Chen, and Shi-Gi Huang, “Power-Efficient Decoder Implementation Based on State Transparent Convolutional Codes,” IET Circuits, Devices & Systems, vol. 6, no. 4, pp. 227-234, July 2012.
36. Li-Yuan Chang, Pei-Yin Chen, Tsang-Yi Wang, and Ching-Sung Chen, “A Low-Cost VLSI Architecture for Robust Distributed Estimation in Wireless Sensor Networks,” IEEE Transactions on Circuits and Systems I-Regular Papers, Jun. 2011.
35. Yeu-Horng Shiau, Pei-Yin Chen, and Chia-Wen Chang “An Area-Efficient Color Demosaicking Scheme for VLSI Architecture,” International Journal of Innovative Computing, Information and Control (IJICIC), Apr. 2011.
34. Pei-Yin Chen, Yi-Ming Lin, Che-Chang Yang “An Efficient Design of Context Modeler for CABAC Encoder in H.264,” IEEE Trans. Very Large Scale Integration Systems, Jun. 2010.
33. Pei-Yin Chen, Li-Yuan Chang, and Tsang-Yi Wang “A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks,” IEEE Transactions on Circuits and Systems I-Regular Papers, Apr. 2010.
32. Pei-Yin Chen and Chih-Yuan Lien “A Novel Image Scaling Algorithm Based On Area-Pixel Model,” International Journal of Innovative Computing, Information and Control (IJICIC), Mar. 2010.
31. Pei-Yin Chen, Chih-Yuan Lien, and Hsu-Ming Chuang, “A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise,” IEEE Trans. Very Large Scale Integration Systems, Mar. 2010.
30. Yi-Ling Hsieh, Pei-Yin Chen and Chih-Yuan Lien “An Efficient Color Interpolation Method For Digital Still Camera,” International Journal of Innovative Computing, Information and Control (IJICIC), October 2009 (SCI)
29. Tsang-Yi Wang, Li-Yuan Chang, and Pei-Yin Chen, “A Collaborative Sensor-Fault Detection Scheme for Robust Distributed Estimation in Sensor Networks,” IEEE Trans. on Communications, October 2009 (SCI)
28. Pei-Yin Chen, Chih-Yuan Lien, and Chi-Pin Lu, “VLSI Implementation of an Edge-Oriented Image Scaling Processor,” IEEE Trans. Very Large Scale Integration Systems, vol. 17, no. 9, pp. 1275-1284, Sept. 2009.
27. Chih-Yuan Lien, Chung-Ping Young, and Pei-Yin Chen,“A Hybrid Image Restoring Algorithm for Interlaced Video,” IEEE Signal Processing Letters, vol. 16, no. 3, pp. 223-226, Mar. 2009.
26. Pei-Yin Chen, Chien-Chuan Huang, Yeu-Horng Shiau, and Yao-Tung Chen, “A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 56, no. 1, Jan. 2009.
25. Pei-Yin Chen and Chih-Yuan Lien, “An Efficient Edge-Preserving Algorithm for Removal of Salt-and-Pepper Noise,” IEEE Signal Processing Letters, vol. 15, pp. 833-836, Dec. 2008.
24. Pei-Yin Chen, Yi-Ming Lin, and Min-Yi Cho, “An Efficient Design of Variable Length Decoder for MPEG-1/2/4,” IEEE Trans. Multimedia, vol. 10, no. 7, pp. 1307-1315, Nov. 2008.
23. Pei-Yin Chen, Ren-Der Chen, Yu-Pin Chang, Leang-San Shieh, and Heidar A. Malki, “Hardware Implementation for Genetic Algorithm,” IEEE Trans. Instrumentation and Measurement, vol. 57, no. 4, pp. 699–705, April 2008 (SCI).
22. Pei-Yin Chen and Yi-Ming Lin, “A Low-Cost VLC Implementation for MPEG-4,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 54, no. 6, pp. 507–511, June 2007 (SCI).
21. Pei-Yin Chen and Yao-Hsien Lai, “A Low-Complexity Interpolation Method for Deinterlacing,” IEICE Trans. on Information and Syst., vol E90-D, no. 2, pp. 606-608, Feb. 2007 (SCI).
20. Pei-Yin Chen and Yi-Ming Lin, “A Low-Cost CAVLC Encoder,”I EICE Trans. on Electronics, vol E89-C, no. 12, pp. 1950-1953, Dec. 2006 (SCI).
19. Pei-Yin Chen and Chao-Tang Yu, “Lossless vector-quantised index coding design and implementation,” IEEE Proc. Circuits Devices Syst., vol. 152, no. 2, pp. 109-117, Apr. 2005 (SCI).
18. Pei-Yin Chen, “VLSI implementation for 1-D multi-level lifting-based wavelet transform,” IEEE Trans. on Computer, vol. 53, no. 4, pp. 386-398, Apr. 2004 (SCI).
17. Pei-Yin Chen, “An efficient prediction algorithm for image vector quantization,” IEEE Trans. on Systems, Man, and Cybernetics, Part B, vol. 34, no. 1, pp. 740-746, Feb. 2004 (SCI).
16. Pei-Yin Chen, “VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform,” IEICE Trans. on Fundamentals, vol. E87-A, no. 1, pp. 275-279, Jan. 2004 (SCI).
15. Pei-Yin Chen and Shung-Chih Chen, “An Efficient VLSI Architecture of 1-D Lifting Discrete Wavelet Transform,” IEICE Trans. on Electronics, vol. E87-C, no. 21, pp. 2009-2014, Nov. 2004 (SCI).
14. Pei-Yin Chen, and Ren-Der Chen, “An index coding algorithm for image vector quantization,” IEEE Trans. on Consumer Electronics, vol. 49, no. 4, pp. 1513-1520, Nov. 2003 (SCI).
13. Pei-Yin Chen, “VLSI implementation for fuzzy membership-function generator,” IEICE Trans. on Information and Syst., vol. E86-D, no. 6, pp. 1122-1125, June 2003 (SCI).
12. Pei-Yin Chen, “A fuzzy search block-matching chip for motion estimation,” Integration, the VLSI Journal, vol. 32, pp. 133-147, Nov. 2002 (SCI).
11. Pei-Yin Chen, “VLSI implementation of lifting discrete wavelet transform using the 5/3 filter,” IEICE Trans. on Information and Syst., pp. 1893-1897, Dec. 2002 (SCI).
10. Pei-Yin Chen, Shung-Chih Chen, Chi-Yung Shao, and Wen-Chu Chen, “An Efficient VLC Coding Algorithm and Its VLSI Architecture,” Journal of Southern Taiwan University of Technology, No. 27, pp. 21-38, Dec. 2002.
9. Jer Min Jou, Yeu-Horng Shiau and Pei-Yin Chen, Shiann-Rong Kuang, “A low cost gray prediction search chip for motion estimation,” IEEE Trans. on Circuits & Syst., Part I, vol. 49, no. 7, pp. 928-938, July 2002 (SCI).
8. Jau-Ling Chen and Pei-Yin Chen, “An efficient gray search algorithm for the estimation of motion vectors,” IEEE Trans. on Systems, Man, and Cybernetics, Part C, vol. 31, no. 2, pp. 242-248, May 2001 (SCI).
7. Pei-Yin Chen and Jer Min Jou, “An efficient blocking-matching algorithm based on fuzzy reasoning,” IEEE Trans. on Systems, Man, and Cybernetics, Part B, vol. 31, no. 2, pp. 253-258, April 2001 (SCI).
6. Yun-Teng Roan and Pei-Yin Chen, “A fuzzy search algorithm for the estimation of motion vectors,” IEEE Trans. on Broadcasting, vol. 46, no. 2, pp. 121-127, 2000 (SCI).
5. Pei-Yin Chen and Jer Min Jou, “Adaptive Arithmetic Coding Using Fuzzy Reasoning and Gray Prediction,” Fuzzy Sets and Syst., vol. 114, no. 2, pp. 239-254, 2000 (SCI).
4. Jer Min Jou, Pei-Yin Chen and Sheng-Fu Yang, “An Adaptive Fuzzy Logic Controller: Its VLSI Architecture and Applications,” IEEE Trans. on VLSI Syst., vol. 8, no. 1, pp. 52-60, 2000 (SCI).
3. Pei-Yin Chen and Jer Min Jou, “A Fast-Search Motion Estimation Method and Its VLSI Architecture,” IEEE Trans. on Circuits Syst., Part II, vol. 46, no. 9, pp. 1233-1240, 1999 (SCI)
2. Jer Min Jou, Pei-Yin Chen and Jian-Ming Sun, “The Grey Prediction Search Algorithm for Block Motion Estimation,” IEEE Trans. on Circuits Syst. Video Technol., vol. 9, no. 6, pp. 843-848, 1999 (SCI).
1. Jer Min Jou and Pei-Yin Chen, “A Fast and Efficient Lossless Data Compression Method,” IEEE Trans. on Communications, vol. 47, no. 9, pp. 1278-1283, 1999 (SCI).
Conference Papers
國際會議
23. Yeu-HorngShiau, Hung-Yu Yang, Pei-Yin Chen, and Chien-Chuan Huang, “High Dynamic Range Image Rendering With Order-Statistics Filter,” Proceedings of IEEE International Conference on Genetic and Evolutionary Computing (ICGEC), 2012, pp. 352-355.
22. Chien-Chuan Huang, Pei-Yin Chen, and Hung-Yu Yang, “A Low-Complexity Scaling Scheme for Barrel Distortion Correction,” Proceedings of IEEE International Conference on Genetic and Evolutionary Computing (ICGEC), 2012, pp-356-359.
21. Yu-Pin Chang, Lemmens, P., Po-Ming Tu, Chien-Chuan Huang, and Pei-Yin Chen, “Cyclic Prefix Optimization for OFDM Transmission over Fading Propagation with Bit-Rate and BER Constraints,” IEEE International Conference on Innovations in Bio-inspired Computing and Applications (IBICA), pp. 29-32, 2011.
20. Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang, Ya-Zhu Zhuang, and Yeu-HorngShiau, “Low Complexity Underwater Image Enhancement Based on Dark Channel Prior,” Proceedings of IEEE International Conference on Innovations in Bio-inspired Computing and Applications (IBICA), 2011, pp. 17-20.
19. Chih-Yuan Lien, Chien-Chuan Huang, Pei-Yin Chen, and Hung-Yu Yang, “An Efficient Denoising Approach for Random-Valued Impulse Noise in Digital Images,” Proceedings of IEEE International Conference on Innovations in Bio-inspired Computing and Applications (IBICA), 2011, pp. 13-16.
18. Hung-Yu Yang, Shang-Yuan Li, Pei-Yin Chen, and Yeu-HorngShiau, “Efficient Color Image Enhancement Based on Fast and Adaptive Bidimensional Empirical Mode Decomposition,” Proceedings of IEEE International Symposium on Computer Science and Society (ISCCS), 2011, pp. 319-322.
17. Chien-Chuan Huang, Chih-Yuan Lien, and Pei-Yin Chen, “A decision-tree-based denoising approach for efficient removal of impulse noise,” IEEE International Symposium on Aware Computing (ISAC), pp. 74-79, 2010.
16. Yeu-HorngShiau, Pei-Yin Chen, Hung-Yu Yang, Yi-Ming Lin, and Shi-Gi Huang, “An Efficient VLSI Architecture for Convolutional Code Decoding,” Proceedings of IEEE International Symposium on Next-Generation Electronics (ISNE), 2010, pp. 223-226.
15. Pei-Yin Chen, Chih-Yuan Lien, and Yi-Ming Lin,“A Real-Time Image Denoising Chip, ” IEEE International Symposium on Circuits and Systems, ISCAS’08, pp. 3390-3393, May 2008.
14. Yi-Ming Lin, Pei-Yin Chen, Chih-Yuan Lien, and Min-Yi Cho, “An Efficient Table-Merging Method for Variable Length Coding,” to be published in IEEE International Conference on Electron Devices and Solid-State Circuits, 2007.
13. Pei-Yin Chen, Chih-Yuan Lien, and Chang-Yan Tsai, “An Effective Impulse Noise Detector of Switching Median Filter using Min-Max Working Window,” to be published in IEEE International Conference on Innovative Computing, Information and Control, 2007.
12. Kai-Sheng Yang, Pei-Yin Chen, Chia-Wen Chang, and Yu-Pin Chang, “A Low-Cost Color Interpolation Method for CCD Digital Still Camera,” IEEE International Conference on Integrated Circuit Design and Technology, pp. 164-167, 2007.
11. Yi-Ming Lin and Pei-Yin Chen, “An efficient implementation of CAVLC for H.264/AVC,” IEEE International Conference on Innovative Computing, Information and Control, pp. 601-604, 2006.
10. Yi-Ming Lin and Pei-Yin Chen, “A low-cost VLSI implementation for VLC,” IEEE International Conference on Industrial Electronics and Applications, pp. 1019-1022, 2006.
9. Ming-Chieh Chung, Shung-Chih Chen, Chao-Tang Yu, and Pei-Yin Chen, “An improvement of fast search algorithm for vector quantization,” IEEE International Conference on Intelligent Signal Processing and Communication Systems, pp. 97-100, 2005.
8. Chia-Hsien Cheng and Pei-Yin Chen, “Design and implementation of lifting discrete wavelet transform,” International Conference on Fundamentals of Electronics Communications and Computer Sciences, Japan, pp. 6.1-6.4, 2002.
7. Che-Yen Hu and Pei-Yin Chen, “An efficient on-line lossless vector-quantized index coder,” International Conference on Fundamentals of Electronics Communications and Computer Sciences, Japan, pp. 20.27-20.30, 2002.
6. Jau-Ling Chen and Pei-Yin Chen, “A fast-search motion estimation method and its VLSI architecture,” IEEE International Conference on Circuits and Systems, pp. 164-167, 2000.
5. Jau-Ling Chen and Pei-Yin Chen, “A new search algorithm for block motion estimation,” IEEE International Conference on Multimedia and Expo (ICME2000), pp. 979-982, 2000.
4. YunTeng Roan and Pei-Yin Chen, “A fast-search motion estimation method,” IEEE International Conference on Systems, Man, and Cybernetics, pp. 1568-1573, 2000.
3. Yeu-Horng Shiau, Pei-Yin Chen and Jer Min Jou, “A gray-based block-matching algorithm and its VLSI architecture,” IEEE International Conference on Signal Processing Systems, pp. 54-63, 1999.
2. Jer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau and Ming-Shiang Liang, “A scalable pipelined architecture for separable 2-D discrete wavelet transform,” IEEE International Conference on Design Automation Conference, pp. 205-208, 1999.
1. Jer Min Jou and Pei-Yin Chen, “An adaptive arithmetic coding method using fuzzy logic and gray theory,” IEEE International Conference on Circuits and Systems, pp. 142-145, 1998.
國內會議
22. 林峻頤, 張郁斌, 陳培殷, “彩色濾波器矩陣內插投射式演算法,” The Proceedings of CETA2006, Taiwan pp.198-199, 2006.
21. 張郁斌, 陳培殷, 蔡鎮陽, “MPEG-4 Simple Profile編碼器於Xilinx Virtex2平台上之軟硬體共同設計與實現,” The Proceedings of NCDC2006, Taiwan pp.252-257, 2006.
20. 楊明勝, 張郁斌, 陳順智, 陳培殷, “改良式高速無失真資料壓縮演算法暨FPGA硬體實現,” The Proceedings of CETA2005, Taiwan pp. 321-327, 2005.
19. 李基泰, 張郁斌, 陳順智, 陳培殷, “可參數化之迴旋/渦輪碼雙模式IP產生器,” The Proceedings of CETA2005, Taiwan pp. 89-95, 2005.
18. 林宜民, 陳順智, 陳培殷, “應用在MPEG-4 的低成本可變長度編碼演算法與其VLSI 架構設計,” The Proceedings of META2005, Taiwan, 2005.
17. 許雲淳, 陳順智, 陳培殷, “VLSI實現低複雜度MPEG-4 Simple Profile編碼系統於嵌入式處理器之SoC平台,” The Proceedings of META2005, Taiwan, 2005.
16. Shian-De Chen, Pei-Yin Chen, Yung-Ming Wang, “A Flexible Genetic Algorithm Chip,” National Computer Symposium, Taiwan pp. 253-257, 2003.
15. Pei-Yin Chen, Shung-Chih Chen and Yung-Ming Wang, “A Flexible VLSI of Genetic Algorithm,” Workshop on Consumer Electronics, Taiwan pp. 50-53, 2003.
14. Wen-Ta Huang, Yi-Heng Chang and Pei-Yin Chen, “VLSI Architecture of 2-D 3-level Lifting-Based Discrete Wavelet Transform,” The Proceedings of CECA2003, Penghu, Taiwan pp. 287-290, 2003.
13. Shiann-Rong Kuang, Yi-Jun Wang and Pei-Yin Chen, “Area Efficient Multipliers Based on Redundant Binary Signed-Digit Booth Encoding for Image Compression,” The Proceedings of CECA2003, Penghu, Taiwan pp. 314-319, 2003.
12. 陳文鉅, 雷朝聖, 陳培殷, “高效率變動長度碼之編解碼硬體實現,” The Proceedings of CECA2003, Penghu, Taiwan pp. 320-325, 2003.
11. Chao-Tang Yu, Pei-Yin Chen and Jia-Kuan Huang, “A Fast Search Algorithm for Image Vector Quantization Using Sum Pyramid of Codewords,” The Proceedings of CECA2003, Penghu, Taiwan pp. 326-331, 2003.
10. 蕭裕益, 陳培殷, “適應性誤差訊號編解碼演算法及其VLSI硬體設計,” The Proceedings of CECA2003, Penghu, Taiwan pp. 332-336, 2003.
9. Pei-Yin Chen, Shiann-Rong Kuang and Chia-Hsien Cheng, “VLSI architecture for lifting discrete wavelet transform,” The 2002 VLSI Design/CAD Symposium, Taiwan, pp. 359-362, 2002.
8. Pei-Yin Chen, Shung-Chih Chen and Che-Yen Hu and, “A lossless vector-quantized index coding method and its VLSI architecture for 2D still image,” The 2002 VLSI Design/CAD Symposium, Taiwan, pp. 472-475, 2002.
7. Yi-Heng Chang and Pei-Yin Chen,“VLSI architecture of 2-D 3-level lifting-based discrete wavelet transform,” Workshop on Consumer Electronics, Taiwan, pp. 47-50, 2002.
6. Chih-Yu Ke and Pei-Yin Chen, “A novel genetic algorithm processor,” Workshop on Consumer Electronics, Taiwan, pp. 55-58, 2002.
5. Ming-He Wang and Pei-Yin Chen,“Two VLSI architectures for fuzzy membership-function generators,” Workshop on Consumer Electronics, Taiwan, pp. 233-236, 2002.
4. Chi-Yung Shao and Pei-Yin Chen, “An efficient class-based VLC decoder,” 17th Technological and Vocational Education Conference of R. O. C., pp. 1379-1386, 2002.
3. Jau-Ling Chen and Pei-Yin Chen, “A fast-search motion estimation method and its VLSI architecture,” Proc. of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 1, pp. 164-167, 2000.
2. Pei-Yin Chen and Shung-Chih Chen, “A new search algorithm for block motion estimation,” 15th Technological and Vocational Education Conference of R. O. C., pp. 155-160, 2000.
1. Shung-Chih Chen and Pei-Yin Chen, “Heuristic block distortion measure in block motion estimation,” 15th Technological and Vocational Education Conference of R. O. C., pp. 209-216, 2000.
專利
周哲民, 陳培殷，”一種使用在影像區塊匹配移動估計的模糊搜尋方法“， 中華民國專利發明第518893號。（期限：92年1月至109年5月）
專書
陳培殷編著，資料壓縮概論，滄海書局，共410頁，2001年(書號EE203, ISBN 957-2079-28-X)。
陳培殷, 劉明穎, 林宜民, 謝怡伶編著，數位IC設計入門—Verilog，滄海書局，2008年(ISBN 978-986-6889-90-5)。
Color Image Test Dataset for Demosaicking
Each image includes UHD resolution images, exposure HD images, and low light levels HD images.